1. Field of the Invention
This invention relates to executing a sequence of instructions on a processor, and more specifically to eliminating dependency conditions such as evil twin conditions.
2. Description of the Related Art
Modern computer processors typically employ an instruction set architecture (ISA) that includes a set of floating-point instructions for performing various floating-point operations. Some instruction set architectures, such as the SPARC ISA, allow a logical floating-point register to be accessed as either a double-precision (DP) register or as two single-precision registers. Processors such as those that implement register renaming may experience a performance penalty when dependent instructions access registers using a combination of single-precision floating-point instructions and double-precision floating-point instructions in the same sequence of instructions.